1. Field of the Invention
The present invention pertains to an output buffer register, and finds applications, in particular, in electronic systems comprising a system bus and functional modules linked to the system bus by way of appropriate communication ports, in particular microprocessors.
2. Description of the Related Art
An output buffer register is a circuit which is intended to be arranged at the output of a functional module, upstream of a communication port of master type which links it to the bus. Its function is to deliver output signals of the functional module.
According to a known design rule applied by the person of ordinary skill in the art, all of the output signals can be delivered on the respective data outputs of flip-flops. This makes it possible to limit the latency introduced at the output.
The micro-architecture of a known output buffer register, in accordance with the diagram of FIG. 1, complies with this design rule.
The output buffer register comprises a single flip-flop register 436 or input register, and an input multiplexer 435.
The register 436 comprises a given number N of flip-flops, each having a data input, a data output and an enable input. The multiplexer 435 comprises N first inputs 435a, N second inputs 435b, N outputs 435c and a selection input 435d. 
The N inputs 435a of the multiplexer respectively receive the N input signals data_in. The N outputs 435c of the multiplexer are respectively linked to the N data inputs of the register 436. The N data outputs 436b of the respective flip-flops of the register 436 deliver N output signals data_out, respectively. These N output signals are moreover delivered on the N inputs 435b of the multiplexer 435.
The N enable inputs 436c of the respective flip-flops of the register 436 receive a clock signal CLK. Moreover, an update_data signal is received on the selection input 435d of the multiplexer 435. This signal is an enable signal which is for example delivered by a state machine.
The register 436 in combination with the multiplexer 435 makes it possible to latch the values of the output signals when the update_data signal is at 0.
This prior art complies with the aforesaid design rule, since the output signals are delivered by data outputs of flip-flops.
On the other hand, the update_data signal drives N enable inputs, namely the inputs 435d of the N flip-flops of the multiplexer 435. This often requires the introduction of what is referred to as a “buffer tree”, which increases the intricacy of the micro-structure and introduces some latency at the input of the buffer register.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.